VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder

V
VLSID
1996
9th International Conference on VLSI Design: VLSI in Mobile Communication
Abstract - VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder

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9th International Conference on VLSI Design: VLSI in Mobile Communication

VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder (PDF)

Bangalore, INDIA

January 03-January 06

ISBN: 0-8186-7228-5

	ASCII Text	x
	Ranjeet Ranade, Sanjay Bhandari, A.N. Chandorkar, "VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder," VLSI Design, International Conference on, pp. 318, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.

	BibTex	x
	@article{ 10.1109/ICVD.1996.489620, author = {Ranjeet Ranade and Sanjay Bhandari and A.N. Chandorkar}, title = {VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1996}, issn = {1063-9667}, pages = {318}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489620}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder SN - 1063-9667 SP EP A1 - Ranjeet Ranade, A1 - Sanjay Bhandari, A1 - A.N. Chandorkar, PY - 1996 KW - Artificial Neural Networks (ANN) KW - Digital Multiplier and Adder KW - VLSI Implementation of Neural Networks VL - 0 JA - VLSI Design, International Conference on ER -

Ranjeet Ranade

Sanjay Bhandari

A.N. Chandorkar

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489620

This paper describes a technique to realize a novel digital multiplier using Artificial Neural Network (ANN). It proposes a generalized `Energy Function' for multiplier and its hard- ware realization by combining conventional digital hardware with a Neural Network. The design of Neurons, Extended range active loads and the digital multiplier are described in this paper along with the simulation results.

Index Terms:

Artificial Neural Networks (ANN), Digital Multiplier and Adder, VLSI Implementation of Neural Networks

Citation:

Ranjeet Ranade, Sanjay Bhandari, A.N. Chandorkar, "VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder," vlsid, pp.318, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996

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