9th International Conference on VLSI Design: VLSI in Mobile Communication A high-speed 32-bit parallel correlator for spread spectrum communication Bangalore, INDIA January 03-January 06 ISBN: 0-8186-7228-5
This paper describes a high speed 32-bit pipelined digital parallel correlator implemented in a Lattice field programmable gate array (FPGA). The parallel correlator is of use in CDMA and spread spectrum transceivers for the continuous calculation of correlation between an incoming data stream with a PN sequence. The maximum frequency of operation of the FPGA based correlator is 87 MHz providing a throughput of one 32-bit correlation every 11.5 ns resulting in considerable improvement over commercially available correlators in terms of speed as well as number of bits. The high speed of operation of the correlator coupled with its ability to handle up to 32 chips per data bit alleviates the problem of low information bit rates due to signal encoding in spread spectrum communication systems. A CMOS integrated circuit implementation of the parallel correlator is presented.
Index Terms:
CMOS digital integrated circuits; correlators; pipeline processing; parallel processing; pseudonoise codes; spread spectrum communication; field programmable gate arrays; radio equipment; digital radio; spread spectrum communication; high speed pipelined digital parallel correlator; lattice field programmable gate array; CDMA; transceiver; PN sequence; data stream; CMOS integrated circuit; 32 bit; 87 MHz; 11.5 ns
Citation:
S. Kulkarni, F. Mazumder, G.I. Haddad, "A high-speed 32-bit parallel correlator for spread spectrum communication," vlsid, pp.313, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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