Design of high performance two stage CMOS cascode op-amps with stable biasing

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9th International Conference on VLSI Design: VLSI in Mobile Communication

Bangalore, INDIA

January 03-January 06

ISBN: 0-8186-7228-5

	ASCII Text	x
	P. Mandal, V. Visvanathan, "Design of high performance two stage CMOS cascode op-amps with stable biasing," VLSI Design, International Conference on, pp. 234, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.

	BibTex	x
	@article{ 10.1109/ICVD.1996.489491, author = {P. Mandal and V. Visvanathan}, title = {Design of high performance two stage CMOS cascode op-amps with stable biasing}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1996}, issn = {1063-9667}, pages = {234}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489491}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Design of high performance two stage CMOS cascode op-amps with stable biasing SN - 1063-9667 SP EP A1 - P. Mandal, A1 - V. Visvanathan, PY - 1996 KW - CMOS analogue integrated circuits; operational amplifiers; circuit analysis computing; integrated circuit design; circuit stability; two stage CMOS cascode op-amps; stable biasing; mirror biasing; output voltage; bias variations; performance metrics; low frequency common mode rejection ratios; power supply rejection ratios; slew rate; systematic offset; circuit simulations VL - 0 JA - VLSI Design, International Conference on ER -

P. Mandal, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India

V. Visvanathan, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489491

The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various performance metrics like low frequency common mode and power supply rejection ratios, slew rate and the sensitivity of the systematic offset are substantially improved. The improved performance is theoretically predicted and substantiated through circuit simulations.

Index Terms:

CMOS analogue integrated circuits; operational amplifiers; circuit analysis computing; integrated circuit design; circuit stability; two stage CMOS cascode op-amps; stable biasing; mirror biasing; output voltage; bias variations; performance metrics; low frequency common mode rejection ratios; power supply rejection ratios; slew rate; systematic offset; circuit simulations

Citation:

P. Mandal, V. Visvanathan, "Design of high performance two stage CMOS cascode op-amps with stable biasing," vlsid, pp.234, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996

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