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9th International Conference on VLSI Design: VLSI in Mobile Communication
An Analytical Delay Model Based on Boolean Process
Bangalore, INDIA
January 03-January 06
ISBN: 0-8186-7228-5
ASCII Text
x 
 
Y. Min, Z. Zhao, Z. Li, "An Analytical Delay Model Based on Boolean Process," VLSI Design, International Conference on, pp. 162, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.1996.489477,
author = {Y. Min and Z. Zhao and Z. Li},
title = {An Analytical Delay Model Based on Boolean Process},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1996},
issn = {1063-9667},
pages = {162},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489477},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - An Analytical Delay Model Based on Boolean Process
SN - 1063-9667
SP
EP
A1 - Y. Min,
A1 - Z. Zhao,
A1 - Z. Li,
PY - 1996
VL - 0
JA - VLSI Design, International Conference on
ER -
 
The concept of Boolean process [1,2] provides an analytical approach to exact delay computation, and enables us to consider delay models more precisely. This paper presents an analytical delay model based-on Boolean process. The analytical delay model manifests its advantages especially when circuits run under high frequency. The model is compared to the traditional delay models. Keyword: Boolean process, waveform polynomial, sensitization, transition delay, floating delay.
Citation:
Y. Min, Z. Zhao, Z. Li, "An Analytical Delay Model Based on Boolean Process," vlsid, pp.162, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996
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