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9th International Conference on VLSI Design: VLSI in Mobile Communication
Clock-Skew Constrained Cell Placement
Bangalore, INDIA
January 03-January 06
ISBN: 0-8186-7228-5
In this paper we propose an object oriented approach for reusing presynthesized components in VLSI design. Each component object has an interface which hides its internal implementation details and yet allows the operations, per-formed by the component, to be invoked by sending an appropriate message. A graph based representation scheme has been adopted for capturing necessary interface information. The proposed interface graph can deal with circuits of various complexities. Moreover, the utilization of the interface graph of an object, during its reuse in sub-sequent synthesis of a new circuit, has been described and illustrated with the help of examples. Lastly, a scheme for extracting the interface graph during synthesis of an object has been proposed. deal with circuits of various complexities. Moreover, the utilization of the interface graph of an object, during its reuse in sub-sequent synthesis of a new circuit, has been described and illustrated with the help of examples. Lastly, a scheme for extracting the interface graph during synthesis of an object has been proposed.
Citation:
V. Natesan, D. Bhatia, "Clock-Skew Constrained Cell Placement," vlsid, pp.146, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996
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