In this paper, we consider Genetic Algorithms for two problems connected with Scan Path Design for VLSI circuits. The first problem, called Partial Scan Path Selection, is to optimize the number of flip-flops to be included in the scan path, at the same time maximizing the fault coverage. The second problem, called Multiple Scan Configuration, is to divide the scan path into a specified number of subchains in order to minimize the test application time. Both problems are combinatorial optimization problems and we show that they lend themselves effectively to a Genetic formulation. Our algorithms have been implemented on a Sun/SPARC in the OASIS design automation environment. We have tested our algorithms on standard benchmarks and the results are encouraging. Compared to other existing methods for scan design, the genetic paradigm is attractive due to its simplicity, potential to generate a global optimal solution, and capability to model compound objective functions.