D.V. Poornaiah, P.V.A. Mohan, "A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications," VLSI Design, International Conference on, pp. 69, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.

@article{ 10.1109/ICVD.1996.489458,
author = {D.V. Poornaiah and P.V.A. Mohan},
title = {A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1996},
issn = {1063-9667},
pages = {69},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489458},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Design, International Conference on
TI - A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications
SN - 1063-9667
SP
EP
A1 - D.V. Poornaiah,
A1 - P.V.A. Mohan,
PY - 1996
KW - VLSI; multiplying circuits; adders; video coding; data compression; computational complexity; digital signal processing chips; VLSI; concurrent dual multiplier-dual adder architecture; video coding applications; high-throughput image coding; carry-save 4:2 compressors; computation time
VL - 0
JA - VLSI Design, International Conference on
ER -