A differential built-in current sensor design for high speed IDDQ testing

V
VLSID
1995
8th International Conference on VLSI Design
Abstract - A differential built-in current sensor design for high speed IDDQ testing

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	Similar Articles Articles by J.P. Hurst Articles by A.D. Singh

8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	J.P. Hurst, A.D. Singh, "A differential built-in current sensor design for high speed IDDQ testing," VLSI Design, International Conference on, pp. 419, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512150, author = {J.P. Hurst and A.D. Singh}, title = {A differential built-in current sensor design for high speed IDDQ testing}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {419}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512150}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A differential built-in current sensor design for high speed IDDQ testing SN - 0-8186-6905-5 SP EP A1 - J.P. Hurst, A1 - A.D. Singh, PY - 1995 KW - built-in self test; integrated circuit testing; electric sensing devices; electric current measurement; CMOS digital integrated circuits; design for testability; integrated circuit design; VLSI; built-in current sensor design; high speed IDDQ testing; differential architecture; quiescent current detection; built-in self-test; BIST environment; n-well technology; MOSIS; 2 micron; 31.25 MHz VL - 0 JA - VLSI Design, International Conference on ER -

J.P. Hurst, Center for Digital Syst. Res., Res. Triangle Inst., Research Triangle Park, NC, USA

A.D. Singh, Center for Digital Syst. Res., Res. Triangle Inst., Research Triangle Park, NC, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512150

A new built-in current sensor design for IDDQ testing is presented in this paper. Our design overcomes performance limitations encountered by previous sensors by using a novel differential architecture which allows early and accurate detection of abnormal quiescent current following the switching transient. A test circuit utilizing the sensor in a built-in self-test environment has been fabricated through MOSIS 2.0-micron n-well technology. At clock speeds of up to 31.65 MHz the sensor accurately detects all six of the defects that were implanted in the test chip.

Index Terms:

built-in self test; integrated circuit testing; electric sensing devices; electric current measurement; CMOS digital integrated circuits; design for testability; integrated circuit design; VLSI; built-in current sensor design; high speed IDDQ testing; differential architecture; quiescent current detection; built-in self-test; BIST environment; n-well technology; MOSIS; 2 micron; 31.25 MHz

Citation:

J.P. Hurst, A.D. Singh, "A differential built-in current sensor design for high speed IDDQ testing," vlsid, pp.419, 8th International Conference on VLSI Design, 1995

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