M. Franklin, Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
K.K. Saluja, Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
K. Kim, Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
Signature analyzers are widely used for compressing test responses. Off-line determination of signatures (for both good circuit and faulty circuits) is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we investigate techniques for speeding up the simulation of multi-input signature registers (MISRs). We first analyze a speedup technique that processes each input independently by table lookups, and show its shortcomings. We then propose a speedup technique that converts the MISR into an equivalent single input circuit. We also present the results of a simulation study that show that this technique achieves a good speedup.
Index Terms:
table lookup; binary sequences; shift registers; logic testing; design for testability; logic design; MISR signatures; fast computation; signature analyzers; test response compression; multi-input signature registers; speedup technique; table lookups; equivalent single input circuit
Citation:
M. Franklin, K.K. Saluja, K. Kim, "Fast computation of MISR signatures," vlsid, pp.414, 8th International Conference on VLSI Design, 1995