Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture

V
VLSID
1995
8th International Conference on VLSI Design
Abstract - Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture

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	Similar Articles Articles by D.V. Poornaiah Articles by P.V.A. Mohan

8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	D.V. Poornaiah, P.V.A. Mohan, "Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture," VLSI Design, International Conference on, pp. 392, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512145, author = {D.V. Poornaiah and P.V.A. Mohan}, title = {Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {392}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512145}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture SN - 0-8186-6905-5 SP EP A1 - D.V. Poornaiah, A1 - P.V.A. Mohan, PY - 1995 KW - VLSI; multiplying circuits; digital arithmetic; parallel architectures; CMOS logic circuits; parallel algorithms; concurrent multiplier-accumulator architecture; VLSI; second order modified Booth algorithm; sign extension bits minimization algorithm; sign-bit updating algorithm; multi-bit recoded parallel multipliers; multiplication; accumulation; computation time reduction; CMOS standard cell technology; 1 micron; 35 ns; 50 pF VL - 0 JA - VLSI Design, International Conference on ER -

D.V. Poornaiah, Transmission R&D, Indian Telephone Ind. Ltd., Bangalore, India

P.V.A. Mohan, Transmission R&D, Indian Telephone Ind. Ltd., Bangalore, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512145

In this paper, we introduce a novel VLSI concurrent multiplier-accumulator (MAC) architecture based on the extension of the widely used second order modified Booth's algorithm. Two efficient algorithms: sign extension bits minimization algorithm (SEBMA) and sign-bit updating algorithm are also presented for minimising the number of sign extension bits to be added and also for dealing with the input operands of arbitrary word-lengths involving different data formats for 3- as well as multi-bit recoded parallel multipliers and MACs. A salient feature of the proposed MAC cell is attributed to its ability in performing the different computations involved : (i) multiplication, (ii) accumulation (add or subtract), (iii) addition of the compensating carry-bits due to the presence of the negative partial product terms and (iv) addition of the minimized number of sign extension bits (computed through SEBMA) concurrently thereby achieving a reduction of 50% in the computation time along with 15% savings in the area when compared with the conventional MAC cells. In order to verify the proposed theory, a 3-bit recoded CMOS 16-gbit MAC cell is designed based on 1 /spl mu/m CMOS standard cell technology rules featuring a worst case cycle time of 35 ns at a capacitive load of 50 pf.

Index Terms:

VLSI; multiplying circuits; digital arithmetic; parallel architectures; CMOS logic circuits; parallel algorithms; concurrent multiplier-accumulator architecture; VLSI; second order modified Booth algorithm; sign extension bits minimization algorithm; sign-bit updating algorithm; multi-bit recoded parallel multipliers; multiplication; accumulation; computation time reduction; CMOS standard cell technology; 1 micron; 35 ns; 50 pF

Citation:

D.V. Poornaiah, P.V.A. Mohan, "Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture," vlsid, pp.392, 8th International Conference on VLSI Design, 1995

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