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8th International Conference on VLSI Design
Resource requirements for field programmable interconnection chips
New Delhi, India
January 04-January 07
ISBN: 0-8186-6905-5
ASCII Text
x 
 
D. Bhatia, J. Haralambides, "Resource requirements for field programmable interconnection chips," VLSI Design, International Conference on, pp. 376, 8th International Conference on VLSI Design, 1995.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.1995.512142,
author = {D. Bhatia and J. Haralambides},
title = {Resource requirements for field programmable interconnection chips},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1995},
isbn = {0-8186-6905-5},
pages = {376},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512142},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Resource requirements for field programmable interconnection chips
SN - 0-8186-6905-5
SP
EP
A1 - D. Bhatia,
A1 - J. Haralambides,
PY - 1995
KW - integrated circuit interconnections; graph theory; network routing; VLSI; field programmable interconnection chips; n-permutation graph; permutation networks; Benes network; network property; routing delays; programmable switches; routing paths; specific I/O permutations; VLSI; user-configured interconnection
VL - 0
JA - VLSI Design, International Conference on
ER -
 
D. Bhatia, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
J. Haralambides, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
In this paper we prove an /spl Omega/(n log n) lower bound on the number of edges of an n-permutation graph G=(V, E). The lower bound is applicable to and characterizes permutations for Field Programmable Interconnection Chips and, more importantly, permutation networks in general. We also propose a family of permutation networks as a variation of the known Benes network with a wide range of diameters, a network property directly related to routing delays. Finally, the relation between the total number of programmable switches and the routing delay (maximum length of routing paths for specific I/O permutations) is explored.
Index Terms:
integrated circuit interconnections; graph theory; network routing; VLSI; field programmable interconnection chips; n-permutation graph; permutation networks; Benes network; network property; routing delays; programmable switches; routing paths; specific I/O permutations; VLSI; user-configured interconnection
Citation:
D. Bhatia, J. Haralambides, "Resource requirements for field programmable interconnection chips," vlsid, pp.376, 8th International Conference on VLSI Design, 1995
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