Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering

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8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	M. Borah, M.J. Irwin, R.M. Owens, "Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering," VLSI Design, International Conference on, pp. 294, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512127, author = {M. Borah and M.J. Irwin and R.M. Owens}, title = {Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {294}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512127}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering SN - 0-8186-6905-5 SP EP A1 - M. Borah, A1 - M.J. Irwin, A1 - R.M. Owens, PY - 1995 KW - CMOS logic circuits; integrated circuit layout; circuit layout CAD; logic CAD; minimisation; circuit optimisation; power consumption minimisation; static CMOS circuits; transistor sizing; input reordering; high fan-out gates; power constrained module generator; PowerSizer; arithmetic circuits; logic circuits VL - 0 JA - VLSI Design, International Conference on ER -

M. Borah, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512127

In this paper we present new techniques to reduce the power consumption of a static CMOS circuit by enlarging transistors in high fan-out gates and reordering inputs to the gates. The techniques are developed based on observations from results of hspice simulations. These methods are incorporated into a performance and power constrained module generator, PowerSizer. Experimental results from the module generator on several real circuits show that as much as 15% saving in power consumption can be obtained on arithmetic circuits with almost no tradeoff in area or delay.

Index Terms:

CMOS logic circuits; integrated circuit layout; circuit layout CAD; logic CAD; minimisation; circuit optimisation; power consumption minimisation; static CMOS circuits; transistor sizing; input reordering; high fan-out gates; power constrained module generator; PowerSizer; arithmetic circuits; logic circuits

Citation:

M. Borah, M.J. Irwin, R.M. Owens, "Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering," vlsid, pp.294, 8th International Conference on VLSI Design, 1995

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