A C-testable modified Booth's array multiplier

V
VLSID
1995
8th International Conference on VLSI Design
Abstract - A C-testable modified Booth's array multiplier

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8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	S.M. Aziz, "A C-testable modified Booth's array multiplier," VLSI Design, International Conference on, pp. 278, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512124, author = {S.M. Aziz}, title = {A C-testable modified Booth's array multiplier}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {278}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512124}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A C-testable modified Booth's array multiplier SN - 0-8186-6905-5 SP EP A1 - S.M. Aziz, PY - 1995 KW - multiplying circuits; digital arithmetic; parallel processing; logic arrays; integrated circuit testing; logic testing; CMOS logic circuits; C-testable multiplier; array multiplier; parallel multiplier; modified Booth algorithm; gate-level design; stuck-at faults VL - 0 JA - VLSI Design, International Conference on ER -

S.M. Aziz, Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512124

In this paper, a C-testable parallel multiplier based on modified Booth's algorithm is presented. The gate-level design requires only 20 vectors to detect all single stuck-at faults. It does not require any extra logic and has no delay overhead compared with the basic non-C-testable design. Five extra inputs are required for the C-testable multiplier, this number can be reached to four using a small amount of extra logic. The multiplier has a regular structure and therefore suitable for use in a silicon compiler.

Index Terms:

multiplying circuits; digital arithmetic; parallel processing; logic arrays; integrated circuit testing; logic testing; CMOS logic circuits; C-testable multiplier; array multiplier; parallel multiplier; modified Booth algorithm; gate-level design; stuck-at faults

Citation:

S.M. Aziz, "A C-testable modified Booth's array multiplier," vlsid, pp.278, 8th International Conference on VLSI Design, 1995

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