Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique

V
VLSID
1995
8th International Conference on VLSI Design
Abstract - Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique

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8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	A.K.B. A'ain, A.H. Bratt, A.P. Dorey, "Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique," VLSI Design, International Conference on, pp. 239, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512116, author = {A.K.B. A'ain and A.H. Bratt and A.P. Dorey}, title = {Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {239}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512116}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique SN - 0-8186-6905-5 SP EP A1 - A.K.B. A'ain, A1 - A.H. Bratt, A1 - A.P. Dorey, PY - 1995 KW - CMOS analogue integrated circuits; integrated circuit testing; fault diagnosis; integrated circuit modelling; analogue CMOS circuits; power supply voltage control testing technique; floating gate defect exposure; power supply voltage sweep; fault coverage; fault detection VL - 0 JA - VLSI Design, International Conference on ER -

A.K.B. A'ain, Dept. of Eng., Lancaster Univ., UK

A.H. Bratt, Dept. of Eng., Lancaster Univ., UK

A.P. Dorey, Dept. of Eng., Lancaster Univ., UK

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512116

In this paper a novel development of a testing technique for analogue integrated circuits based on sweeping the power supply voltage is described. It is shown that by using a simple floating gate fault model together with the proposed scheme it is possible to achieve a high fault coverage. The scope of work discussed in this paper is focused on exposing floating gate defects which, using other methods, usually requires careful and accurate knowledge of the elements, including parasitic components, of the equivalent circuit of the devices.

Index Terms:

CMOS analogue integrated circuits; integrated circuit testing; fault diagnosis; integrated circuit modelling; analogue CMOS circuits; power supply voltage control testing technique; floating gate defect exposure; power supply voltage sweep; fault coverage; fault detection

Citation:

A.K.B. A'ain, A.H. Bratt, A.P. Dorey, "Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique," vlsid, pp.239, 8th International Conference on VLSI Design, 1995

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