8th International Conference on VLSI Design Efficient simulation of interconnect and mixed analog-digital circuits in ACES New Delhi, India January 04-January 07 ISBN: 0-8186-6905-5
Adaptively Controlled Explicit Simulation (ACES) is a new timing simulation technique for the analysis of integrated circuits and systems. This paper describes various techniques for the enhancement of ACES to the simulation of analog, mixed analog-digital and interconnect circuits. Firstly, the use of AWE macromodels in ACES is proposed for efficient and accurate simulation of interconnect circuits with nonlinear terminations. Circuit topology constraints are removed in ACES by using efficient techniques for the simulation of loops of capacitors and floating capacitors. The use of variable accuracy device models is proposed for accurate simulation of analog and mixed analog/digital circuits. These enhancements make ACES an efficient solution to problems previously regarded as domain of conventional circuit simulators, like SPICE, which are too expensive for most practical applications.
Index Terms:
circuit analysis computing; mixed analogue-digital integrated circuits; analogue integrated circuits; integrated circuit interconnections; timing; transient analysis; ACES; adaptively controlled explicit simulation; timing simulation; mixed analog-digital circuits; analog circuit simulation; interconnect circuit simulation; AWE macromodels; nonlinear terminations; variable accuracy device models; circuit topology constraints removal; transient simulation
Citation:
A. Devgan, R.A. Rohrer, "Efficient simulation of interconnect and mixed analog-digital circuits in ACES," vlsid, pp.229, 8th International Conference on VLSI Design, 1995 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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