JAGUAR: a high speed VLSI chip for JPEG image compression standard

V
VLSID
1995
8th International Conference on VLSI Design
Abstract - JAGUAR: a high speed VLSI chip for JPEG image compression standard

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8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	M. Kovac, P. Ranganathan, "JAGUAR: a high speed VLSI chip for JPEG image compression standard," VLSI Design, International Conference on, pp. 220, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512112, author = {M. Kovac and P. Ranganathan}, title = {JAGUAR: a high speed VLSI chip for JPEG image compression standard}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {220}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512112}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - JAGUAR: a high speed VLSI chip for JPEG image compression standard SN - 0-8186-6905-5 SP EP A1 - M. Kovac, A1 - P. Ranganathan, PY - 1995 KW - digital signal processing chips; CMOS digital integrated circuits; data compression; image coding; pipeline processing; parallel architectures; VLSI; discrete cosine transforms; entropy codes; image colour analysis; Huffman codes; JAGUAR; high speed VLSI chip; JPEG image compression standard; pipelined single chip VLSI architecture; high throughput; discrete cosine transform; entropy encoder; clock rate; input rate; color images; CMOS VLSI chip; Huffman entropy coding; 100 MHz; 1024 pixel; 1048576 pixel VL - 0 JA - VLSI Design, International Conference on ER -

M. Kovac, Fac. of Electr. Eng., Zagreb Univ., Croatia

P. Ranganathan, Fac. of Electr. Eng., Zagreb Univ., Croatia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512112

In this paper, we describe a fully pipelined single chip VLSI architecture for implementing the JPEG baseline image compression standard The architecture exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The entire architecture can be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024/spl times/1024 color images. Currently, a prototype CMOS VLSI chip implementing the proposed architecture is being designed.

Index Terms:

digital signal processing chips; CMOS digital integrated circuits; data compression; image coding; pipeline processing; parallel architectures; VLSI; discrete cosine transforms; entropy codes; image colour analysis; Huffman codes; JAGUAR; high speed VLSI chip; JPEG image compression standard; pipelined single chip VLSI architecture; high throughput; discrete cosine transform; entropy encoder; clock rate; input rate; color images; CMOS VLSI chip; Huffman entropy coding; 100 MHz; 1024 pixel; 1048576 pixel

Citation:

M. Kovac, P. Ranganathan, "JAGUAR: a high speed VLSI chip for JPEG image compression standard," vlsid, pp.220, 8th International Conference on VLSI Design, 1995

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