Testability-oriented channel routing

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	Similar Articles Articles by J. Khare Articles by S. Mitra Articles by P.K. Nag Articles by U. Maly Articles by R. Rutenbar

8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	J. Khare, S. Mitra, P.K. Nag, U. Maly, R. Rutenbar, "Testability-oriented channel routing," VLSI Design, International Conference on, pp. 208, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512110, author = {J. Khare and S. Mitra and P.K. Nag and U. Maly and R. Rutenbar}, title = {Testability-oriented channel routing}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {208}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512110}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Testability-oriented channel routing SN - 0-8186-6905-5 SP EP A1 - J. Khare, A1 - S. Mitra, A1 - P.K. Nag, A1 - U. Maly, A1 - R. Rutenbar, PY - 1995 KW - integrated circuit testing; integrated circuit layout; network routing; design for testability; fault diagnosis; circuit optimisation; integrated circuit yield; circuit layout CAD; IC testing quality; testability-oriented channel routing; design strategies; IC layout modification; test escape probability; iterative channel routing tool; fault detectability; bridging fault; fault undetectability; yield loss; WrenTR VL - 0 JA - VLSI Design, International Conference on ER -

J. Khare, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

S. Mitra, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

P.K. Nag, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

U. Maly, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

R. Rutenbar, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512110

The quality of IC testing can be improved by applying appropriate design strategies. In this paper, we present a testability-oriented routing methodology, which can be used to modify the IC layout so as to reduce the probability of test escape. A testability-oriented iterative channel routing tool based on this methodology has been developed. Example applications of this tool illustrating the methodology are also presented in the paper.

Index Terms:

integrated circuit testing; integrated circuit layout; network routing; design for testability; fault diagnosis; circuit optimisation; integrated circuit yield; circuit layout CAD; IC testing quality; testability-oriented channel routing; design strategies; IC layout modification; test escape probability; iterative channel routing tool; fault detectability; bridging fault; fault undetectability; yield loss; WrenTR

Citation:

J. Khare, S. Mitra, P.K. Nag, U. Maly, R. Rutenbar, "Testability-oriented channel routing," vlsid, pp.208, 8th International Conference on VLSI Design, 1995

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