A graph approach to DFT hardware placement for robust delay fault BIST

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	Similar Articles Articles by I.P. Shaik Articles by M.L. Bushnell

8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	I.P. Shaik, M.L. Bushnell, "A graph approach to DFT hardware placement for robust delay fault BIST," VLSI Design, International Conference on, pp. 177, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512100, author = {I.P. Shaik and M.L. Bushnell}, title = {A graph approach to DFT hardware placement for robust delay fault BIST}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {177}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512100}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A graph approach to DFT hardware placement for robust delay fault BIST SN - 0-8186-6905-5 SP EP A1 - I.P. Shaik, A1 - M.L. Bushnell, PY - 1995 KW - design for testability; integrated circuit testing; delays; built-in self test; logic testing; digital integrated circuits; fault location; graph theory; ULSI; graph heuristic; DFT hardware placement; robust delay fault BIST; ULSI circuit; built-in self-testing model; design for testability hardware; hazard free structure VL - 0 JA - VLSI Design, International Conference on ER -

I.P. Shaik, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA

M.L. Bushnell, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512100

In order to test a ULSI circuit robustly and less expensively for delay faults we proposed a robust delay-fault built-in self-testing model. Long pattern simulation times and excessive hardware overhead have been a concern in our model. We propose a graph heuristic to optimally place Design for Testability (DFT) hardware in order to eliminate hazards in TEST mode. This technique produces a circuit structure that is hazard free for any single-bit changing sequence and reduces the CPU time drastically as we avoid pattern simulation. We collapse the new PI's and PO's added to the circuit and this reduces the hardware overhead significantly.

Index Terms:

design for testability; integrated circuit testing; delays; built-in self test; logic testing; digital integrated circuits; fault location; graph theory; ULSI; graph heuristic; DFT hardware placement; robust delay fault BIST; ULSI circuit; built-in self-testing model; design for testability hardware; hazard free structure

Citation:

I.P. Shaik, M.L. Bushnell, "A graph approach to DFT hardware placement for robust delay fault BIST," vlsid, pp.177, 8th International Conference on VLSI Design, 1995

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