VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes

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8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	L. Penzo, D. Sciuto, C. Silvano, "VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes," VLSI Design, International Conference on, pp. 156, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512096, author = {L. Penzo and D. Sciuto and C. Silvano}, title = {VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {156}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512096}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes SN - 0-8186-6905-5 SP EP A1 - L. Penzo, A1 - D. Sciuto, A1 - C. Silvano, PY - 1995 KW - error correction codes; error detection codes; VLSI; parallel processing; decoding; integrated logic circuits; application specific integrated circuits; digital integrated circuits; hardware description languages; logic CAD; VLSI design; odd-weight-column byte error detection; SEC-DED codes; single error correction; double error detection; single byte error detection; SEC-DED-SBD codes; high performances VLSI implementations; high speed encoding/decoding circuits; parallel data manipulation; software tool; VHSIC Hardware Description Language; VHDL description VL - 0 JA - VLSI Design, International Conference on ER -

L. Penzo, Dipartimento di Elettronica, Politecnico di Milano, Italy

D. Sciuto, Dipartimento di Elettronica, Politecnico di Milano, Italy

C. Silvano, Dipartimento di Elettronica, Politecnico di Milano, Italy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512096

The paper introduces an extension to previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes. The proposed approach constructs systematic odd-weight-column SEC-DED-SBD codes whose corrigible errors also include any odd number of erroneous bits per byte. The main purpose of this paper is to show that the proposed codes are suitable for high performances VLSI implementations in computer applications, using high speed encoding/decoding circuits and parallel data manipulation. Furthermore, the paper shows how such codes can be easily designed from the specifications using a software tool, which generates the VHDL (VHSIC Hardware Description Language) description of the circuits.

Index Terms:

error correction codes; error detection codes; VLSI; parallel processing; decoding; integrated logic circuits; application specific integrated circuits; digital integrated circuits; hardware description languages; logic CAD; VLSI design; odd-weight-column byte error detection; SEC-DED codes; single error correction; double error detection; single byte error detection; SEC-DED-SBD codes; high performances VLSI implementations; high speed encoding/decoding circuits; parallel data manipulation; software tool; VHSIC Hardware Description Language; VHDL description

Citation:

L. Penzo, D. Sciuto, C. Silvano, "VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes," vlsid, pp.156, 8th International Conference on VLSI Design, 1995

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