S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M.P. Pareek, R. Gupta, "A single chip, pipelined, cascadable, multichannel, signal processor," VLSI Design, International Conference on, pp. 150, 8th International Conference on VLSI Design, 1995.

@article{ 10.1109/ICVD.1995.512095,
author = {S. Krishnakumar and P. Suresh and S. Sadashiva Rao and M.P. Pareek and R. Gupta},
title = {A single chip, pipelined, cascadable, multichannel, signal processor},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1995},
isbn = {0-8186-6905-5},
pages = {150},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512095},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Design, International Conference on
TI - A single chip, pipelined, cascadable, multichannel, signal processor
SN - 0-8186-6905-5
SP
EP
A1 - S. Krishnakumar,
A1 - P. Suresh,
A1 - S. Sadashiva Rao,
A1 - M.P. Pareek,
A1 - R. Gupta,
PY - 1995
KW - digital signal processing chips; pipeline processing; delay lines; timing; VLSI; CMOS digital integrated circuits; single chip signal processor; pipelined processor; cascadable processor; multichannel signal processor; DSP architecture; array multipliers; programmable delay line; memory mapped peripheral; online diagnostics; shadow accumulators; double metal CMOS process; 144 pin CPGA; 2 micron
VL - 0
JA - VLSI Design, International Conference on
ER -