A new switching-level approach to multiple-output functions synthesis

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	Similar Articles Articles by C. Bolchini Articles by G. Buonanno Articles by D. Sciuto Articles by R. Stefanelli

8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	C. Bolchini, G. Buonanno, D. Sciuto, R. Stefanelli, "A new switching-level approach to multiple-output functions synthesis," VLSI Design, International Conference on, pp. 125, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512090, author = {C. Bolchini and G. Buonanno and D. Sciuto and R. Stefanelli}, title = {A new switching-level approach to multiple-output functions synthesis}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {125}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512090}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A new switching-level approach to multiple-output functions synthesis SN - 0-8186-6905-5 SP EP A1 - C. Bolchini, A1 - G. Buonanno, A1 - D. Sciuto, A1 - R. Stefanelli, PY - 1995 KW - minimisation of switching nets; CMOS logic circuits; logic CAD; integrated circuit layout; circuit layout CAD; multivalued logic circuits; switching-level; multiple-output functions synthesis; transistor level; area minimization; timing constraints; figures of merit; randomly generated functions VL - 0 JA - VLSI Design, International Conference on ER -

C. Bolchini, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy

G. Buonanno, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy

D. Sciuto, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy

R. Stefanelli, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512090

A new methodology for multiple-output functions synthesis at transistor level is presented. The final network produces the defined output values by creating a set of connections among source, ground and output nodes not necessarily implementing specific subcircuits constituting each single function. Area minimization and timing constraints are figures of merit for the quality of the proposed solution. Application results for a set of randomly generated functions are also reported.

Index Terms:

minimisation of switching nets; CMOS logic circuits; logic CAD; integrated circuit layout; circuit layout CAD; multivalued logic circuits; switching-level; multiple-output functions synthesis; transistor level; area minimization; timing constraints; figures of merit; randomly generated functions

Citation:

C. Bolchini, G. Buonanno, D. Sciuto, R. Stefanelli, "A new switching-level approach to multiple-output functions synthesis," vlsid, pp.125, 8th International Conference on VLSI Design, 1995

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