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8th International Conference on VLSI Design
Parallel test generation with low communication overhead
New Delhi, India
January 04-January 07
ISBN: 0-8186-6905-5
ASCII Text
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S. Venkatraman, S. Seth, P. Agrawal, "Parallel test generation with low communication overhead," VLSI Design, International Conference on, pp. 116, 8th International Conference on VLSI Design, 1995.
 
 
BibTex
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@article{ 10.1109/ICVD.1995.512088,
author = {S. Venkatraman and S. Seth and P. Agrawal},
title = {Parallel test generation with low communication overhead},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1995},
isbn = {0-8186-6905-5},
pages = {116},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512088},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Parallel test generation with low communication overhead
SN - 0-8186-6905-5
SP
EP
A1 - S. Venkatraman,
A1 - S. Seth,
A1 - P. Agrawal,
PY - 1995
KW - combinational circuits; logic testing; Boolean functions; software performance evaluation; processor scheduling; parallel algorithms; shared memory systems; parallel test generation; low communication overhead; combinational logic; boolean satisfiability; dynamic search-space allocation strategy; greedy heuristic; analytical model; Sequent multiprocessor; shared memory multiprocessor
VL - 0
JA - VLSI Design, International Conference on
ER -
 
S. Venkatraman, LSI Logic Corp., Milpitas, CA, USA
S. Seth, LSI Logic Corp., Milpitas, CA, USA
P. Agrawal, LSI Logic Corp., Milpitas, CA, USA
In this paper we present a method of parallelizing test generation for combinational logic using boolean satisfiability. We propose a dynamic search-space allocation strategy to split work between the available processors. This strategy is easy to implement with a greedy heuristic and is economical in its demand for inter-processor communication. We derive an analytical model to predict the performance of the parallel versus sequential implementations. The effectiveness of our method and analysis is demonstrated by an implementation on a Sequent (shared memory) multiprocessor. The experimental data shows significant performance improvement in parallel implementation, validates our analytical model, and allows predictions of performance for a range of time-out limits and degrees of parallelism.
Index Terms:
combinational circuits; logic testing; Boolean functions; software performance evaluation; processor scheduling; parallel algorithms; shared memory systems; parallel test generation; low communication overhead; combinational logic; boolean satisfiability; dynamic search-space allocation strategy; greedy heuristic; analytical model; Sequent multiprocessor; shared memory multiprocessor
Citation:
S. Venkatraman, S. Seth, P. Agrawal, "Parallel test generation with low communication overhead," vlsid, pp.116, 8th International Conference on VLSI Design, 1995
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