MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level

V
VLSID
1995
8th International Conference on VLSI Design
Abstract - MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level

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8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	S. Yadavalli, I. Pomeranz, S.M. Reddy, "MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level," VLSI Design, International Conference on, pp. 110, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512087, author = {S. Yadavalli and I. Pomeranz and S.M. Reddy}, title = {MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {110}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512087}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level SN - 0-8186-6905-5 SP EP A1 - S. Yadavalli, A1 - I. Pomeranz, A1 - S.M. Reddy, PY - 1995 KW - combinational circuits; logic testing; scheduling; automatic testing; integrated circuit testing; MUSTC-testing; multi-stage-combinational test; test scheduling; register-transfer level; automatic test; control paths; data-paths; signal types; module level pre-computed test sets VL - 0 JA - VLSI Design, International Conference on ER -

S. Yadavalli, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512087

In this paper we discuss a new automatic test scheduling system for architectures that use separate control and data-paths. MUlti-STage-Combinational Testing (MUSTC-Testing) at the Register-Transfer Level significantly eases test generation and can be used in lieu of or to complement sequential test generation at the gate level. We provide a system with eleven signal types to perform test scheduling at the RT level which allows module level pre-computed test sets to be directly used for testing. A test scheduler is then described along with the results obtained.

Index Terms:

combinational circuits; logic testing; scheduling; automatic testing; integrated circuit testing; MUSTC-testing; multi-stage-combinational test; test scheduling; register-transfer level; automatic test; control paths; data-paths; signal types; module level pre-computed test sets

Citation:

S. Yadavalli, I. Pomeranz, S.M. Reddy, "MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level," vlsid, pp.110, 8th International Conference on VLSI Design, 1995

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