Functional clock schedule optimization

V
VLSID
1995
8th International Conference on VLSI Design
Abstract - Functional clock schedule optimization

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	Similar Articles Articles by A. Saldanha Articles by N.V. Shenoy Articles by R.K. Brayton Articles by A.L. Sangiovanni-Vincentelli

8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	A. Saldanha, N.V. Shenoy, R.K. Brayton, A.L. Sangiovanni-Vincentelli, "Functional clock schedule optimization," VLSI Design, International Conference on, pp. 93, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512084, author = {A. Saldanha and N.V. Shenoy and R.K. Brayton and A.L. Sangiovanni-Vincentelli}, title = {Functional clock schedule optimization}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {93}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512084}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Functional clock schedule optimization SN - 0-8186-6905-5 SP EP A1 - A. Saldanha, A1 - N.V. Shenoy, A1 - R.K. Brayton, A1 - A.L. Sangiovanni-Vincentelli, PY - 1995 KW - clocks; scheduling; delays; flip-flops; sequential circuits; timing; circuit optimisation; clock schedule optimization; delays; latches; false paths; time frames; level-sensitive sequential circuits VL - 0 JA - VLSI Design, International Conference on ER -

A. Saldanha, California Univ., Berkeley, CA, USA

N.V. Shenoy, California Univ., Berkeley, CA, USA

R.K. Brayton, California Univ., Berkeley, CA, USA

A.L. Sangiovanni-Vincentelli, California Univ., Berkeley, CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512084

All existing algorithms for clock schedule optimization are conservative since they use only topological analysis to estimate the delays of paths between latches. This paper proposes a novel algorithm that accounts for false paths (over several time frames) in level-sensitive sequential circuits to obtain tighter bounds on the optimum clock schedule than previously obtainable.

Index Terms:

clocks; scheduling; delays; flip-flops; sequential circuits; timing; circuit optimisation; clock schedule optimization; delays; latches; false paths; time frames; level-sensitive sequential circuits

Citation:

A. Saldanha, N.V. Shenoy, R.K. Brayton, A.L. Sangiovanni-Vincentelli, "Functional clock schedule optimization," vlsid, pp.93, 8th International Conference on VLSI Design, 1995

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