8th International Conference on VLSI Design
Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs
New Delhi, India
January 04-January 07
ISBN: 0-8186-6905-5
A. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
R.K. Gorai, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
V.V.S.S. Raju, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
The introduction of multiplexer based FPGAs has renewed interest in logic design using multiplexers. This paper presents an iterative approach for the synthesis of combinational circuits using a tree network of 2-to-1 multiplexers. A characterizing parameter of Boolean functions, known as Ratio Parameters, has been used in each iteration to reduce the search space. The obtained multiplexer network is then mapped onto the Actel ACT1 FPGA basic blocks. The performance of the proposed approach has been evaluated by comparing the results of 11 MCNC benchmark problems with the results of the existing technology mappers.
Index Terms:
multiplexing; multiplexing equipment; field programmable gate arrays; combinational circuits; logic CAD; iterative methods; Boolean functions; VLSI; multiplexer network; ratio parameters; FPGAs; logic design; iterative approach; combinational circuits; tree network; Boolean functions; search space; Actel ACT1; MCNC benchmark problems
Citation:
A. Pal, R.K. Gorai, V.V.S.S. Raju, "Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs," vlsid, pp.63, 8th International Conference on VLSI Design, 1995
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