A fast-multiplier generator for FPGAs

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	Similar Articles Articles by S. Kumar Articles by K. Forward Articles by M. Palaniswami

8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	S. Kumar, K. Forward, M. Palaniswami, "A fast-multiplier generator for FPGAs," VLSI Design, International Conference on, pp. 53, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512077, author = {S. Kumar and K. Forward and M. Palaniswami}, title = {A fast-multiplier generator for FPGAs}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {53}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512077}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A fast-multiplier generator for FPGAs SN - 0-8186-6905-5 SP EP A1 - S. Kumar, A1 - K. Forward, A1 - M. Palaniswami, PY - 1995 KW - multiplying circuits; field programmable gate arrays; neural chips; parallel architectures; fast-multiplier generator; FPGAs; artificial neural networks; variable word length multipliers; Booth encoded optimized Wallace tree architecture; FPGA architecture VL - 0 JA - VLSI Design, International Conference on ER -

S. Kumar, Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia

K. Forward, Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia

M. Palaniswami, Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512077

FPGA implementation of artificial neural networks calls for multipliers of various word length. In this paper, a new algorithm for generating variable word length multipliers for FPGA implementation is presented. The multipliers generated are based on a Booth Encoded optimized Wallace tree architecture. Several features of FPGA architecture are used to generate fast and efficient multipliers. These multipliers are shown to be 20% faster than existing FPGA multiplier implementations.

Index Terms:

multiplying circuits; field programmable gate arrays; neural chips; parallel architectures; fast-multiplier generator; FPGAs; artificial neural networks; variable word length multipliers; Booth encoded optimized Wallace tree architecture; FPGA architecture

Citation:

S. Kumar, K. Forward, M. Palaniswami, "A fast-multiplier generator for FPGAs," vlsid, pp.53, 8th International Conference on VLSI Design, 1995

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