8th International Conference on VLSI Design Functional test generation for non-scan sequential circuits New Delhi, India January 04-January 07 ISBN: 0-8186-6905-5
The feasibility of generating high quality functional test vectors for sequential circuits using the Growth (G) and Disappearance (D) fault model has been demonstrated earlier. In this paper we provide a theoretical validation of the G and D fault model by proving the ability of this model to guarantee complete stuck fault coverage in combinational and sequential circuits synthesized employing algebraic transformations. We also provide experimental results on a wide range of synthesized FSMs. A comparison with a state-of-the-art gate level ATPG tool demonstrates the efficiency and limitation of the functional approach.
Index Terms:
logic testing; sequential circuits; fault diagnosis; finite state machines; VLSI; integrated circuit testing; automatic testing; functional test generation; nonscan sequential circuits; functional test vectors; growth and disappearance fault model; complete stuck fault coverage; algebraic transformations; synthesized FSMs
Citation:
M.K. Srinivas, J. Jacob, V.D. Agrawal, "Functional test generation for non-scan sequential circuits," vlsid, pp.47, 8th International Conference on VLSI Design, 1995 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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