loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
8th International Conference on VLSI Design
Functional test generation for non-scan sequential circuits
New Delhi, India
January 04-January 07
ISBN: 0-8186-6905-5
ASCII Text
x 
 
M.K. Srinivas, J. Jacob, V.D. Agrawal, "Functional test generation for non-scan sequential circuits," VLSI Design, International Conference on, pp. 47, 8th International Conference on VLSI Design, 1995.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.1995.512076,
author = {M.K. Srinivas and J. Jacob and V.D. Agrawal},
title = {Functional test generation for non-scan sequential circuits},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1995},
isbn = {0-8186-6905-5},
pages = {47},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512076},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Functional test generation for non-scan sequential circuits
SN - 0-8186-6905-5
SP
EP
A1 - M.K. Srinivas,
A1 - J. Jacob,
A1 - V.D. Agrawal,
PY - 1995
KW - logic testing; sequential circuits; fault diagnosis; finite state machines; VLSI; integrated circuit testing; automatic testing; functional test generation; nonscan sequential circuits; functional test vectors; growth and disappearance fault model; complete stuck fault coverage; algebraic transformations; synthesized FSMs
VL - 0
JA - VLSI Design, International Conference on
ER -
 
M.K. Srinivas, CAD Lab./SERC, Indian Inst. of Sci., Bangalore, India
J. Jacob, CAD Lab./SERC, Indian Inst. of Sci., Bangalore, India
V.D. Agrawal, CAD Lab./SERC, Indian Inst. of Sci., Bangalore, India
The feasibility of generating high quality functional test vectors for sequential circuits using the Growth (G) and Disappearance (D) fault model has been demonstrated earlier. In this paper we provide a theoretical validation of the G and D fault model by proving the ability of this model to guarantee complete stuck fault coverage in combinational and sequential circuits synthesized employing algebraic transformations. We also provide experimental results on a wide range of synthesized FSMs. A comparison with a state-of-the-art gate level ATPG tool demonstrates the efficiency and limitation of the functional approach.
Index Terms:
logic testing; sequential circuits; fault diagnosis; finite state machines; VLSI; integrated circuit testing; automatic testing; functional test generation; nonscan sequential circuits; functional test vectors; growth and disappearance fault model; complete stuck fault coverage; algebraic transformations; synthesized FSMs
Citation:
M.K. Srinivas, J. Jacob, V.D. Agrawal, "Functional test generation for non-scan sequential circuits," vlsid, pp.47, 8th International Conference on VLSI Design, 1995
Usage of this product signifies your acceptance of the Terms of Use.