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8th International Conference on VLSI Design
Robust testing for stuck-at faults
New Delhi, India
January 04-January 07
ISBN: 0-8186-6905-5
T.J. Chakraborty, AT&T Bell Labs., Princeton, NJ, USA
V.D. Agrawal, AT&T Bell Labs., Princeton, NJ, USA
This paper proposes a generalization of robust tests with respect to assumptions about fault models and circuit models. The specific case of d-robust tests for single stuck-at faults is studied. These tests maintain their validity in the presence of macro-delay faults. A macro-delay of size n means that the delay of all combinational paths can be in the range [O,nT] where T is the clock period. We give a simple method of duplicating a test vector n times to produce a d-robust test for a stuck-at fault in a combinational circuit. We further implement a more complex algorithm to derive d-robust tests for stuck-at faults in sequential circuits.
Index Terms:
combinational circuits; logic testing; sequential circuits; fault diagnosis; delays; logic circuit testing; robust testing; fault models; circuit models; d-robust tests; single stuck-at faults; combinational circuit; sequential circuits
Citation:
T.J. Chakraborty, V.D. Agrawal, "Robust testing for stuck-at faults," vlsid, pp.42, 8th International Conference on VLSI Design, 1995
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