A fast algorithm to test planar topological routability

V
VLSID
1995
8th International Conference on VLSI Design
Abstract - A fast algorithm to test planar topological routability

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8th International Conference on VLSI Design

New Delhi, India

January 04-January 07

ISBN: 0-8186-6905-5

	ASCII Text	x
	A. Lim, S. Sahni, V. Thanvantri, "A fast algorithm to test planar topological routability," VLSI Design, International Conference on, pp. 8, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512069, author = {A. Lim and S. Sahni and V. Thanvantri}, title = {A fast algorithm to test planar topological routability}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {8}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512069}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A fast algorithm to test planar topological routability SN - 0-8186-6905-5 SP EP A1 - A. Lim, A1 - S. Sahni, A1 - V. Thanvantri, PY - 1995 KW - network routing; network topology; integrated circuit layout; circuit layout CAD; VLSI; fast algorithm; planar topological routability testing; linear time algorithm; pin nets; single layer routing; VLSI layout; IC layout design VL - 0 JA - VLSI Design, International Conference on ER -

A. Lim, Information Technol. Inst., Singapore, Singapore

S. Sahni, Information Technol. Inst., Singapore, Singapore

V. Thanvantri, Information Technol. Inst., Singapore, Singapore

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512069

We develop a simple linear time algorithm to determine if a collection of two pin nets can be routed, topologically, in a plane (i.e. single layer). Experiments indicate that this algorithm is faster than the linear time algorithm of Marek-Sadowska and Tarng (1983).

Index Terms:

network routing; network topology; integrated circuit layout; circuit layout CAD; VLSI; fast algorithm; planar topological routability testing; linear time algorithm; pin nets; single layer routing; VLSI layout; IC layout design

Citation:

A. Lim, S. Sahni, V. Thanvantri, "A fast algorithm to test planar topological routability," vlsid, pp.8, 8th International Conference on VLSI Design, 1995

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