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2007 International Conference on Parallel Processing (ICPP 2007)
Loop-level Speculative Parallelism in Embedded Applications
Xi'an, China
September 10-September 14
ISBN: 0-7695-2933-X
ASCII Text
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Mafijul Md. Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenstrom, "Loop-level Speculative Parallelism in Embedded Applications," Parallel Processing, International Conference on, pp. 3, 2007 International Conference on Parallel Processing (ICPP 2007), 2007.
 
 
BibTex
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@article{ 10.1109/ICPP.2007.53,
author = {Mafijul Md. Islam and Alexander Busck and Mikael Engbom and Simji Lee and Michel Dubois and Per Stenstrom},
title = {Loop-level Speculative Parallelism in Embedded Applications},
journal ={Parallel Processing, International Conference on},
volume = {0},
year = {2007},
issn = {0190-3918},
pages = {3},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICPP.2007.53},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Processing, International Conference on
TI - Loop-level Speculative Parallelism in Embedded Applications
SN - 0190-3918
SP
EP
A1 - Mafijul Md. Islam,
A1 - Alexander Busck,
A1 - Mikael Engbom,
A1 - Simji Lee,
A1 - Michel Dubois,
A1 - Per Stenstrom,
PY - 2007
KW - null
VL - 0
JA - Parallel Processing, International Conference on
ER -
 
Mafijul Md. Islam, Chalmers University of Technology, Sweden
Alexander Busck, Chalmers University of Technology, Sweden
Mikael Engbom, Chalmers University of Technology, Sweden
Simji Lee, University of Southern California, Los Angeles, USA
Michel Dubois, University of Southern California, Los Angeles, USA
Per Stenstrom, Chalmers University of Technology, Sweden
As multi-core microprocessors are becoming widely adopted, the need to extract thread-level parallelism (TLP) from single-threaded applications in a seamless fashion increases. In this paper, we characterize the nature of TLP in embedded applications and study the limits of performance speedup using parallelizing compilers on platforms with and without support for thread-level speculation.

First and somewhat expected, only two out of ten applications from the consumer and telecom domains of the EEMBC suite could be automatically parallelized on multi-core architectures without thread-level speculation (TLS) support. We systematically study the speedup obtained by parallelizing compiler technologies by factoring in the impact of the number of cores, thread decomposition strategies, and thread-management overhead. Overall, we have found that a TLS substrate is critical to uncover thread level parallelism and thread-management overhead must be low. On an eight-way multi-core system, it is possible to achieve a speedup of four, on average, for six out of the ten applications of EEMBC which we have analyzed.

Citation:
Mafijul Md. Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenstrom, "Loop-level Speculative Parallelism in Embedded Applications," icpp, pp.3, 2007 International Conference on Parallel Processing (ICPP 2007), 2007
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