Third International Conference on Systems (icons 2008) Power-Aware Test Framework for Network-on-Chip April 13-April 18 ISBN: 978-0-7695-3105-2
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICONS.2008.49
In this paper, we propose the power-aware test framework for Network-on-Chip (NoC). First, the possibility of using embedded processor and on-chip network are introduced and evaluated with benchmark system to test the other embedded cores. Second, a new generation method of test pattern, which is called ‘don’t care mapping’, is presented to reduce the power consumption of on-chip network. The experimental results show that the power consumption is reduced up to 8% at the communication components.
Index Terms:
test, NoC, low-power
Citation:
Byung-Gyu Ahn, Jun-Mo Jung, Jong-Wha Chong, "Power-Aware Test Framework for Network-on-Chip," icons, pp.103-107, Third International Conference on Systems (icons 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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