As multi-core systems begin to appear, their possible applications, parallel performance and on-chip interconnection networks have to be clarified, analyzed and optimized. The paper investigates an impact of collective communication (CC) overhead that may be critical for performance of parallel applications. Two potential topologies of networks on chip (NoC) are investigated, a ring-based network and 2D-mesh, due to their easy manufacturability on a chip. The wormhole switching, full duplex links and 1-port non-combining as well as combining nodes are considered. The lower bounds on the number of communication steps and upper bounds of CC times based on real CC algorithms are given. They can be evaluated for any given start-up time and link bandwidth. This enables performance prediction of applications with CCs among computing nodes.