2006 IEEE International Conference on Multimedia and Expo
Complexity Analysis of H.264 Decoder for FPGA Design
Toronto, ON, Canada
July 09-July 12
ISBN: 1-4244-0366-7
Tuomas Lindroth, Dept. of Information Technology, Communication Systems Laboratory, University of Turku, Turku, Finland. E-mail: tuomas.lindroth@utu.fi
Nastooh Avessta, Dept. of Information Technology, Communication Systems Laboratory, University of Turku, Turku, Finland. E-mail: nastooh.avessta@utu.fi@utu.fi
Jukka Teuhola, Dept. of Information Technology, Communication Systems Laboratory, University of Turku, Turku, Finland. E-mail: jukka.teuhola@utu.fi
Tiberiu Seceleanu, Dept. of Information Technology, Communication Systems Laboratory, University of Turku, Turku, Finland. E-mail: tiberiu.seceleanu@utu.fi
A major challenge in the design of any real time system is the proper selection of implementation and platform alternatives. In this paper, a suitable FPGA-based design of the H.264 decoder is presented. Since H.264 standard only specifies the syntax and semantics of the video stream and not the video codec itself, the selection process may be directed based upon the temporal complexity of different parts of the decoder. Here, we present the process flow of these parts using basic algebraic operators. The analysis of the required logic elements to implement the decoder, on various platforms, is presented.
Citation:
Tuomas Lindroth, Nastooh Avessta, Jukka Teuhola, Tiberiu Seceleanu, "Complexity Analysis of H.264 Decoder for FPGA Design," icme, pp.1253-1256, 2006 IEEE International Conference on Multimedia and Expo, 2006
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