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2006 IEEE International Conference on Multimedia and Expo
A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing
Toronto, ON, Canada
July 09-July 12
ISBN: 1-4244-0366-7
ASCII Text
x 
 
Yao-chang Yang, Chien-chang Lin, Hsui-cheng Chang, Ching-lung Su, Jiun-in Guo, "A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing," Multimedia and Expo, IEEE International Conference on, pp. 357-360, 2006 IEEE International Conference on Multimedia and Expo, 2006.
 
 
BibTex
x
 
@article{ 10.1109/ICME.2006.262510,
author = {Yao-chang Yang and Chien-chang Lin and Hsui-cheng Chang and Ching-lung Su and Jiun-in Guo},
title = {A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing},
journal ={Multimedia and Expo, IEEE International Conference on},
volume = {0},
year = {2006},
isbn = {1-4244-0366-7},
pages = {357-360},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICME.2006.262510},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Multimedia and Expo, IEEE International Conference on
TI - A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing
SN - 1-4244-0366-7
SP357
EP360
A1 - Yao-chang Yang,
A1 - Chien-chang Lin,
A1 - Hsui-cheng Chang,
A1 - Ching-lung Su,
A1 - Jiun-in Guo,
PY - 2006
KW - null
VL - 0
JA - Multimedia and Expo, IEEE International Conference on
ER -
 
Yao-chang Yang, Dept. of Computer Science and Information Engineering, National Chung Cheng University, Chia-Yi 621, Taiwan, ROC. e-mail: yangyc@cs.ccu.edu.tw
Chien-chang Lin, Dept. of Computer Science and Information Engineering, National Chung Cheng University, Chia-Yi 621, Taiwan, ROC. e-mail: lcc@cs.ccu.edu.tw
Hsui-cheng Chang, Dept. of Computer Science and Information Engineering, National Chung Cheng University, Chia-Yi 621, Taiwan, ROC. e-mail: chc92@cs.ccu.edu.tw
Ching-lung Su, Department of Electronics Engineering, National Yunlin University of Science Technology, Yun-Lin 640, Taiwan, ROC. e-mail: kevinsu@yuntech.edu.tw
Jiun-in Guo, Dept. of Computer Science and Information Engineering, National Chung Cheng University, Chia-Yi 621, Taiwan, ROC. e-mail: jiguo@cs.ccu.edu.tw
In this paper we present a high throughput VLSI architecture design for Context-based Adaptive Binary Arithmetic Decoding (CABAD) in MPEG-4 AVC/H.264. To speed-up the inherent sequential operations in CABAD, we break down the processing bottleneck by proposing a look-ahead codeword parsing technique on the segmenting context tables with cache registers, which averagely reduces up to 53% of cycle count. Based on a 0.18- m CMOS technology, the proposed design outperforms the existing design by both reducing 40% of hardware cost and achieving about 1.6 times data throughput at the same time.
Citation:
Yao-chang Yang, Chien-chang Lin, Hsui-cheng Chang, Ching-lung Su, Jiun-in Guo, "A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing," icme, pp.357-360, 2006 IEEE International Conference on Multimedia and Expo, 2006
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