loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
2006 IEEE International Conference on Multimedia and Expo
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application
Toronto, ON, Canada
July 09-July 12
ISBN: 1-4244-0366-7
ASCII Text
x 
 
Yu-han Chen, Tung-chien Chen, Liang-gee Chen, "Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application," Multimedia and Expo, IEEE International Conference on, pp. 281-284, 2006 IEEE International Conference on Multimedia and Expo, 2006.
 
 
BibTex
x
 
@article{ 10.1109/ICME.2006.262453,
author = {Yu-han Chen and Tung-chien Chen and Liang-gee Chen},
title = {Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application},
journal ={Multimedia and Expo, IEEE International Conference on},
volume = {0},
year = {2006},
isbn = {1-4244-0366-7},
pages = {281-284},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICME.2006.262453},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Multimedia and Expo, IEEE International Conference on
TI - Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application
SN - 1-4244-0366-7
SP281
EP284
A1 - Yu-han Chen,
A1 - Tung-chien Chen,
A1 - Liang-gee Chen,
PY - 2006
KW - null
VL - 0
JA - Multimedia and Expo, IEEE International Conference on
ER -
 
Yu-han Chen, DSP/IC Design Lab, Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan. doliamo@video.ee.ntu.edu.tw, djchen@vid
Tung-chien Chen, DSP/IC Design Lab, Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan. doliamo@video.ee.ntu.edu.tw, djchen@vid
Liang-gee Chen, DSP/IC Design Lab, Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan. Email: lgchen@video.ee.ntu.edu.tw, doli
In this paper, a power-scalable H.264 encoding system is provided with the efforts on both the algorithm and the architecture levels. For a start, a Motion Estimation (ME) preskip algorithm is adopted as a system-level power-scalable algorithm. In order to realize a dedicated hardware, a novel reconfigurable Macro-Block (MB) pipelining architecture is proposed. It can improve not only system flexibility but also hardware efficiency. Besides, it is also beneficial for power management with module-level gated clock insertion. According to simulation results, the proposed H. 264 encoder can support power-scalable functionality in the range of about 20 to 90 mW with graceful quality degradation.
Citation:
Yu-han Chen, Tung-chien Chen, Liang-gee Chen, "Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application," icme, pp.281-284, 2006 IEEE International Conference on Multimedia and Expo, 2006
Usage of this product signifies your acceptance of the Terms of Use.