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2005 IEEE International Conference on Multimedia and Expo
Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction
Amsterdam, Netherlands
July 06-July 06
ISBN: 0-7803-9331-7
null Min Li, Institute of VLSI Design, Zhejiang Univ., P. R. China; Microsoft Research Asia; School of Information Science and Engineering, Zhejiang Univ., P. R. China, limin@imec.be
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicated hardware such as ASIC based accelerator. Dynamical Voltage Scaling (DVS) is one of the most efficient techniques to promote the energy efficiency. Most existing papers on this topic use simple heuristics to predict processor load, and poor prediction accuracy is observed in experiments. We advocate intensive analysis on processor load before designing DVS framework and algorithm. Hence, we conduct load analysis on more than 600 processor load trace files for 57 test sequences and 98 representative clips from Internet. Basic statistical analysis and time series analysis are applied intensively to identify major characteristics of the processor load. The analysis shows that it is feasible to predict processor load using low order linear time series model if the load is sampled using feature period. Moreover, there is indeed significant potential to reduce the energy consumption. Based on the analysis results, we develop a fully adaptive DVS technique to adjust supply voltage online with controllable penalty.
Citation:
null Min Li, null Xiaobo Wu, null Zihua Guo, R. Yao, null Xiaolang Yan, "Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction," icme, pp.1480-1483, 2005 IEEE International Conference on Multimedia and Expo, 2005
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