6th IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007) Split Private and Shared L2 Cache Architecture for Snooping-based CMP Melbourne, Australia July 11-July 13 ISBN: 0-7695-2841-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICIS.2007.172
Cache access latency and efficient usage of on-chip capacity are critical factors that affect the performance of the chip multiprocessor (CMP) architecture. In this paper, we propose a SPS2 cache architecture and cache coherence protocol for snooping-based CMP, in which each processor has both private and shared L2 cache to balance latency and capacity. Our protocol is expressed in a new state graph form, through which we prove our protocol by formal verification method. Simulation experiments shows that the SPS2 structure outperforms private L2 and shared L2 structure.
Citation:
Xuemei Zhao, Karl Sammut, Fangpo He, Shaowen Qin, "Split Private and Shared L2 Cache Architecture for Snooping-based CMP," icis, pp.900-905, 6th IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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