First International Conference on Innovative Computing, Information and Control - Volume III (ICICIC'06) Design of a Scalable Computer Cluster for MPEG-4 Parallel Encoder Beijing, China August 30-September 01 ISBN: 0-7695-2616-0
This paper describes a architecture of homogeneous computer cluster for the parallel encoder of the natural video section of the MPEG-4 specification. The parallel encoder on this architecture can lower the negative impact on the achieved speed-up under high resolution input video data that has large communication overhead. Experimental results show that the proposed architecture is featured with scalability and has higher CPU utilization and speedup than general architecture of homogeneous computer cluster.
Citation:
Po-Kai Chiu, Wen-Yu Su, Chih-Ping Chu, "Design of a Scalable Computer Cluster for MPEG-4 Parallel Encoder," icicic, vol. 3, pp.597-600, First International Conference on Innovative Computing, Information and Control - Volume III (ICICIC'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||