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First International Conference on Innovative Computing, Information and Control - Volume II (ICICIC'06)
Application of DDR Controller for High-speed Data Acquisition Board
Beijing, China
August 30-September 01
ISBN: 0-7695-2616-0
Zude Zhou, Wuhan University of Technology, China
Songlin Cheng, Wuhan University of Technology, China
Quan Liu, Wuhan University of Technology, China
DDR SDRAM (Double Data Rate Synchronously Dynamic RAM) controller is discussed in this paper. The principle and commands of FPGA-based DDR SDRAM controller are detailed. The R/W control of DDR SDRAM is realized through Verilog HDL, and this controller is applied into 400MHz single channel high-speed, high-precision and large-capacity data acquisition board.
Citation:
Zude Zhou, Songlin Cheng, Quan Liu, "Application of DDR Controller for High-speed Data Acquisition Board," icicic, vol. 2, pp.611-614, First International Conference on Innovative Computing, Information and Control - Volume II (ICICIC'06), 2006
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