In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing application specific networks on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or Multistage Interconnection Network MIN). A complete graph is constructed such that each vertex represents an IP core or a set of IP cores connecting by a locally synchronous bus (or cross-bar or MIN) and each edge has a weight (profit) representing a communication ratio (CR) for each pair of vertices. A maximal-profit spanning tree is constructed to represent the final network on chip. Comparisons on cost and total communication times with the SPIN architecture, mesh architecture, and binary tree architecture using Huffman-coding-like algorithm show that the new methodology has better results.