Abstract: A key design parameter for embedded SIMD architectures is the amount of image data directly mapped to each processing element, defined as the pixel-per-processing-element (PPE) ratio. This paper presents a study to determine the effect of different PPE mapping on the performance and efficiency figures of an embedded SIMD architecture. The correlation between problem size, PPE ratio, and processing element architecture will be illustrated for a target implementation in 100 nm technology. A case study is illustrated to derive quantitative measures of performance, energy, and area efficiency. For fixed image size, power consumption, and silicon area a constrained optimization is performed that indicates that a PPE value of 4 yields to the most efficient system configuration. Results indicate that this system is capable to deliver performance in excess of 1 Tops/s at 2.4 W, operating at 200 MHz, with 16,384 PEs integrated in about 850 mm2.