This paper presents the hardware architectures of two texture features: mean and contrast. These features are based on the co-occurrence matrix method. However, the features can be calculated without the co-occurrence matrix, too. The formalism behind the features without the co-occurrence matrix is shown, and the corresponding hardware architectures are depicted with Data Flow Graphs (DFG). The architecture was developed with Very high speed integrated circuit Hardware Description Language (VHDL) and commercially available logic synthesis tool by Synopsis. The VHDL code was synthesized to Xilinx XC4000-series FPGA library.