In today?s system-on-chip (SOC) design process heterogeneous technology cores are integrated at several layers of hierarchy. Hence, multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical SOCs that contain earlier generation SOCs as embedded megacores. Unlike previous works that mostly assumes flat test hierarchy, the proposed technique considers the design hierarchy constraints for the cores in case of non-interactive design transfer between core vendor and core user. The proposed SOC test scheduling technique is used to minimize the test application time for the hierarchical SOCs. Experimental results are presented for three ITC?02 benchmark circuits containing megacores and results shown 55% improvement over recently proposed methods for hierarchical SOC test scheduling.