Operating CMOS circuits with power supplies below the threshold voltage has been suggested for ultra-low power systems. High fan-in or fan-out circuits, such as those in memories, are prone to failure when operating in this regime. Vanishing noise margins due to reduced transistor on-to-off current ratios result in circuit failure as the supply voltage shrinks. Therefore, design guidelines for robust subthreshold logic circuit are developed in this paper. First, an analytical model is derived to determine a circuit?s fan-in/out limitations and the minimum supply voltage for robust subthreshold operation. Excellent agreement between the analytical model and circuit simulations is shown. This model is applied to the analysis of circuit robustness as affected by design choices, both systematic and random processing variations, supply voltage fluctuations, and temperature variations.