2005 International Conference on Computer Design Low-Power Design of 90-nm SuperH Processor Core San Jose, California October 02-October 05 ISBN: 0-7695-2451-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.72
A low power Super H embedded processor core, the SH-X2, has been desogned in 90-nm CMOS tehnology. The power consumption was reduced by using hierarchical fined grained clock gating to reduce the power consumption of the flip-flops and clock-tree synthesis and layout that support implementation of the clock gating, and several-level power evaluations for FTL refinement. With this clock gating and RTL refinement the power consumption of the clock-tree and flip-flops was reduced by 35% and 59%, including the process shrinking effects, respectively. As a result, the SH-X2 achieved 6,000 MIPS/W using Renesas low-power process with lowered voltage. Its performance efficiency was 25% better than that of a 130-nm-process SH-X.
Citation:
Tetsuya Yamaday, Masahide Abe, Yusuke Nitta, Kenji Oguray, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Tak ada, Fumio Arakawa, Osamu Nishii, T oshihiro Hattori, "Low-Power Design of 90-nm SuperH Processor Core," iccd, pp.258-266, 2005 International Conference on Computer Design, 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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