2005 International Conference on Computer Design
A Feasibility Study of Subthreshold SRAM Across Technology Generations
San Jose, California
October 02-October 05
ISBN: 0-7695-2451-6
DOI Bookmark:
http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.7
Abstract: In this paper we have explored the feasibility of designing an SRAM array in the subthreshold domain of device operation. We have performed a nominal corner analysis of power and stability and a statistical analysis of the different failure probablilities of the subthreshold SRAM. Our analysis shows that subthreshold SRAM gives significant reduction (~100X) of operating amd standby power at iso-performance (~100MHz) compared to the superthreshold counterpart. However, with increasing intra-die variation owing to technology scaling, the failure probability of subthreshold SRAM increases thereby masking the power benefits.
Citation:
Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy, "A Feasibility Study of Subthreshold SRAM Across Technology Generations," iccd, pp.417-424, 2005 International Conference on Computer Design, 2005
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