2005 International Conference on Computer Design Architectural Considerations for Energy Efficiency San Jose, California October 02-October 05 ISBN: 0-7695-2451-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.26
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay and energy behaviors of gates and complex circuits due to supply scaling and circuit optimization on a modified test setup accounting for routing cost. The energy-throughput relationships of both pipelining and parallelism are characterized in connection to their corresponding depth and degree, showing clear advantages of pipelining over parallelism.
Citation:
Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdija, "Architectural Considerations for Energy Efficiency," iccd, pp.13-16, 2005 International Conference on Computer Design, 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||