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2005 International Conference on Computer Design
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors
San Jose, California
October 02-October 05
ISBN: 0-7695-2451-6
James Tschanz, ECE Dept., Northwestern University, Evanston, IL, USA
Yibin Ye, ECE Dept., Northwestern University, Evanston, IL, USA
Yehea Ismail, ECE Dept., Northwestern, University, Evanston, IL,
This paper purposes a bus architecture called Skewed Repeater Bus (SRB) for reducing on-chip interconnect energy in microprocessors. By introducing relative delay between neighboring bus lines, SRB reduces both average and worst-case coupling capacitance between those lines. SRB is compared to previously published techniques like Delayed Data Bus (DDB) and Delayed Clock Bus (DCB). Simulation results in 65-nm process show that bus energy reduction of 18% is achieved when SRB is applied to a real microprocessor example, versus 11% and 7% only for DDB and DCB; respectively.
Citation:
Muhammad Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea Ismail, "A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors," iccd, pp.253-257, 2005 International Conference on Computer Design, 2005
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