At-Speed Logic BIST Architecture for Multi-Clock Designs

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	Similar Articles Articles by Laung-Terng Wang Articles by Xiaoqing Wen Articles by Po-Ching Hsu Articles by Shianling Wu Articles by Jonhson Guo

2005 International Conference on Computer Design

San Jose, California

October 02-October 05

ISBN: 0-7695-2451-6

	ASCII Text	x
	Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo, "At-Speed Logic BIST Architecture for Multi-Clock Designs," Computer Design, International Conference on, pp. 475-478, 2005 International Conference on Computer Design, 2005.

	BibTex	x
	@article{ 10.1109/ICCD.2005.119, author = {Laung-Terng Wang and Xiaoqing Wen and Po-Ching Hsu and Shianling Wu and Jonhson Guo}, title = {At-Speed Logic BIST Architecture for Multi-Clock Designs}, journal ={Computer Design, International Conference on}, volume = {0}, year = {2005}, isbn = {0-7695-2451-6}, pages = {475-478}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.119}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - At-Speed Logic BIST Architecture for Multi-Clock Designs SN - 0-7695-2451-6 SP475 EP478 A1 - Laung-Terng Wang, A1 - Xiaoqing Wen, A1 - Po-Ching Hsu, A1 - Shianling Wu, A1 - Jonhson Guo, PY - 2005 KW - null VL - 0 JA - Computer Design, International Conference on ER -

Laung-Terng Wang, SynTest Technologies, Inc.

Xiaoqing Wen, Kyushu Institute of Technology, Japan

Po-Ching Hsu, SynTest Technologies, Inc., Taiwan

Shianling Wu, SynTest Technologies, Inc.

Jonhson Guo, SynTest Technologies, Inc., China

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.119

This paper presents an at-speed logic BIST architecture for testing multi-clock, multi-frequency designs. The scheme employed allows true at-speed test quality for circuits containing multiple clocks without any clock frequency manipulation. Physical implementation is easily achieved due to the use of a low-speed scan enable (SE) signal and reduced timing-critical design requirements. Application results for two industrial designs are also reported.

Citation:

Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo, "At-Speed Logic BIST Architecture for Multi-Clock Designs," iccd, pp.475-478, 2005 International Conference on Computer Design, 2005

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