We propose a virtual supply rail control technique that reduces SRAM leakage. This method encompasses a cell-based image, serial tiling, pitch matching, small drive device overhead, and controlled power-on currents while incurring small circuit overhead. A virtual rail cell contains both the sleep transistor fingers and input/output drive transistors. The usual overhead associated with the drive circuit that controls the sleep transistors is significantly reduced due to reduced wire load and improved drive efficiency. This technique provides gradual power-on characteristics and good signal slews while effectively mitigating leakage current, maintaining read/write speed and achieving power-on latency compatible with high-performance designs.